Programmable logic devices (“PLDs”) (also sometimes referred to as PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, or FPGAs), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits; however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to not necessarily exclude such devices.
Like all integrated circuits, programmable logic devices are susceptible to manufacturing defects. In order to increase yields, programmable logic devices may be provided with spare or redundant circuits. In a repairable region, each respective row below a bad row, including the spare row, have programmable connections that can be used to replicate the pattern of connections in the row above that respective row. See, for example, U.S. Pat. Nos. 6,201,404 and 6,344,755.
A programmable logic device is typically made up of logic regions, such as logic array blocks (LABs), which in turn comprise logic elements. Signals are routed to and from the logic regions over vertical and horizontal conductors that form signal paths. Particular circuitry, including, for example, pass gates, multiplexors (“muxes”), and drivers may be used to couple and drive signals onto horizontal or vertical wires, or to receive signals from the horizontal or vertical wires and drive them to the logic regions. Circuitry forming connections between horizontal wires, vertical wires, and logic regions may be programmable. One example of a programmable connection is a pass gate coupled to a random access memory bit circuit, the pass gate programmably connecting a vertical wire to an input multiplexor of a logic region. The pass gate is open or closed depending on the data in the memory bit. However, that is just one example. Some examples may include connections based upon static or dynamic random access memory, electrically erasable read-only memory, flash, fuse, and anti-fuse programmable connections. The programmable connection could also be implemented through mask programming during fabrication of the device. While mask programming may have disadvantages relative to some of the field programmable options already listed, it may be useful in certain high Volume applications.
Horizontal wires may form signal paths that typically exist within, or are associated with, a particular logic region row. Thus, in a row-based redundancy scheme, if a spare row is utilized, the horizontal wires and associated connections to and from logic regions of a row above the spare row are replaced by those of the spare row. Vertical wires typically span several rows, or may even span all the rows on a device. Past PLDs with redundancy have had vertical wires that span all or half of the device. Repairable regions that are no larger than the length of a vertical wire rely on connections to and from the same vertical wire in each row within the repairable region.